As integrated circuit processing techniques improve, a reduction in the feature sizes of memory devices is desired in order to increase the density of the IC circuits and memory arrays. The feature size of memory devices may be limited by the device's characteristics rather than the minimum feature size that the process is capable reaching. In NAND Flash memory arrays, for example, as the channel length and the spacing between memory cells in memory strings are reduced, a minimum size is reached that is primarily dictated by the operational characteristics of the floating gate memory cells that make up the memory strings.
NAND architecture memory strings and memory arrays formed by vertical NAND memory cells have been created to increase the density of memory devices. Vertical NAND memory architecture known in the art comprises a single physical cell per memory node. Prior art fabrication techniques have failed to increase the physical memory cell/memory node ratio, thus limiting the cell density of NAND architecture memory strings and memory arrays.
The descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.